[2019/03/16 update]
最新消息是這個新團隊工作地點不侷限 (台灣/上海/美國/...)
目前也在找團隊Leader, 所以我或許需要再調整下述的待遇上限,
但這真的很看人,所以我就先不改了,總之有意願的人請不要猶豫將履歷寄給我.
[公司名稱] 美商超微半導體台灣分公司
[職缺名稱] SDX-USB/PCIE IP design工程師
[徵求條件]
工作內容
- Develop micro-architecture for USB blocks based on architectural
requirement.
- Develop RTL code for USB blocks in Verilog HDL and make sure functional
correct and
reusable for different configuration.
- Synthesis and deliver netlist that meeting timing, area and power
requirement. Help
PD on the floor planning and close timing.
- Analyze gating efficiency report to improve RTL quality.
Job Requirements:
- MS degree of EE with 10+ years working experience in ASIC Company.
- Expert of Verilog RTL design and has experience of large digital ASIC
project.
- Familiar with front-end EDA tools and flows.
- Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.)
- Fluent English on talking, presentation and writing documents.
- Work is performed with limited supervision. Strong sense of task
scheduling and
deliver on time as predetermined milestones committed to manager.
- Can solves complex, novel and non-recurring problems; initiates
significant changes to
existing processes/methods and leads development and implementation.
-Possesses specialized knowledge of computer architecture and computer
arithmetic.
- Possesses specialized knowledge of PCIE and AMBA.
- Possesses specialized knowledge of USB and Thunderbolt (a plus)..
[工作型態]
周休二日 外商管理
並上海團隊密切合作
[待遇]
年薪保守預估200W NTD以上,
依照個人能力與學經歷調整,
如果您夠優秀, 數字可能 >> 200 (200~500)
[聯絡方式]
請將履歷寄至 [email protected]
這是一個外商難得的RTL designer在台灣的職缺,
還有其他很不錯的福利,
有興趣想了解更多的朋友,請再私訊我
--
最新消息是這個新團隊工作地點不侷限 (台灣/上海/美國/...)
目前也在找團隊Leader, 所以我或許需要再調整下述的待遇上限,
但這真的很看人,所以我就先不改了,總之有意願的人請不要猶豫將履歷寄給我.
[公司名稱] 美商超微半導體台灣分公司
[職缺名稱] SDX-USB/PCIE IP design工程師
[徵求條件]
工作內容
- Develop micro-architecture for USB blocks based on architectural
requirement.
- Develop RTL code for USB blocks in Verilog HDL and make sure functional
correct and
reusable for different configuration.
- Synthesis and deliver netlist that meeting timing, area and power
requirement. Help
PD on the floor planning and close timing.
- Analyze gating efficiency report to improve RTL quality.
Job Requirements:
- MS degree of EE with 10+ years working experience in ASIC Company.
- Expert of Verilog RTL design and has experience of large digital ASIC
project.
- Familiar with front-end EDA tools and flows.
- Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.)
- Fluent English on talking, presentation and writing documents.
- Work is performed with limited supervision. Strong sense of task
scheduling and
deliver on time as predetermined milestones committed to manager.
- Can solves complex, novel and non-recurring problems; initiates
significant changes to
existing processes/methods and leads development and implementation.
-Possesses specialized knowledge of computer architecture and computer
arithmetic.
- Possesses specialized knowledge of PCIE and AMBA.
- Possesses specialized knowledge of USB and Thunderbolt (a plus)..
[工作型態]
周休二日 外商管理
並上海團隊密切合作
[待遇]
年薪保守預估200W NTD以上,
依照個人能力與學經歷調整,
如果您夠優秀, 數字可能 >> 200 (200~500)
[聯絡方式]
請將履歷寄至 [email protected]
這是一個外商難得的RTL designer在台灣的職缺,
還有其他很不錯的福利,
有興趣想了解更多的朋友,請再私訊我
--
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