CAD與Layout - 工程師

Table of Contents

目前有兩個職務選擇...想聽聽各位鄉民的意見!!
1.IC Layout 工程師
工作內容不外乎就是大家所想的那樣!

2.CAD工程師
1.RTL to GDSII IC Implementation based on Synopsys Tools:
包括: Synthesis (DC), Equivalence-Check (FM), Design-for Testability(DFTC),
Static-Timing Analysis(PT), Place & Route(ICC), Clock-Tree-Synthesis,
RC Extraction(Star-RC), Cross-Talk Fixing(PTSI), IR-Drop/EM Analysis,
Dynamic/Leakage Power Optimization, DFM and Multi-Voltage Low-Power Design(UPF),
LVS/DRC, … etc.
2.Physical Verificationꀠbased on Calibre tools:
. Physical Verification (LVS / DRC / ...etc)
. Commandfile maintenance (Calibre DRC/LVS/PERC , Star RC extraction )
. Physical Verification flow enhancement. ( New commandfile coding / PV environment coding. )

對未來發展..各位比較推哪邊呢!?

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All Comments

Leila avatarLeila2013-04-23
當然是Cad, 大公司最好,小公司得包山包海
Tristan Cohan avatarTristan Cohan2013-04-26
會CAD通常都會layout但會layout不見得會CAD這樣你清楚了吧
Aaliyah avatarAaliyah2013-04-29
選CAD,但我不認為會CAD就會layout。layout很重經驗值
Brianna avatarBrianna2013-04-30
是為什麼大家都這樣選擇???
Kelly avatarKelly2013-05-03
選CAD以後"或許"有機會跳到IC設計。layout永遠就只能layout
而且現在數位IC的layout已經被APR蠶食了!
Caroline avatarCaroline2013-05-04
謝謝M大如此的解說!!我已經瞭解了!!!
Ethan avatarEthan2013-05-08
類比layout依舊無法被取代
Rae avatarRae2013-05-09
CAD是爽缺 layout是使缺 根本不能比阿
Iris avatarIris2013-05-12
P大為何這樣說呢!?
Charlotte avatarCharlotte2013-05-16
這個職缺內容好眼熟喔...
Eden avatarEden2013-05-16
CAD怎會爽缺,時間壓力來至於RD與ECO,還有QA能不能達到
Edward Lewis avatarEdward Lewis2013-05-18
Lib.pre., timing分析,還有cmd的熟悉度,處理Error能力
Ethan avatarEthan2013-05-18
TapeOut壓力以及PV最後修DRC, LVS都是壓力好嘛.....
Hardy avatarHardy2013-05-21
恭喜阿滴 可喜可賀
Olga avatarOlga2013-05-26
如果是APR vs analog layout 選APR