Cisco誠徵ASIC designer/verification - 福利

代PO, 勿站內信!!

<公司名稱>
Cisco

<工作地點>
台北市11052信義路四段460號12樓
履歷請寄：Jackie Su [email protected]

<薪資福利>
薪資: 月薪新台幣15萬元起~12個月(依個人經歷調整)
獎金：視個人績效與公司營運
特休假：一年13天（帶薪病假及彈休另計）, 生日假1天, 公益假5天, 緊急事假4周

<職缺>
○ Senior ASIC designer
< Experience Required >
‧ 5 - 10 years in ASIC experience. Network ASIC experience is a plus.
‧ Strong tracking record of ASIC design from concept to mass production
‧ Hands-on experience on Verilog HDL coding.
‧ Experience of high performance ASIC design flow from specification to
system bringing up
‧ Highly motivated, positive, detail oriented and responsible
‧ Good team player and good communication skills
‧ MSEE/MSCS

○ Senior ASIC verification
< Experience Required >
‧ 5 - 10 years in ASIC design verification.
‧ Hands-on experience on Verilog HDL verification
‧ Experience of high performance ASIC design flow from specification to
system bringing up
‧ Knowledge of System Verilog and UVM verification methodology
‧ Highly motivated, positive, detail oriented and responsible
‧ Good team player and good communication skills
‧ MSEE/MSCS

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