Intel PSG (Altera) 徵entry level DV - 海外工作

Yedda avatar
By Yedda
at 2018-03-03T10:26

Table of Contents


隔壁經理要我再來貼一次...


歡迎即將畢業或剛畢業的EE同學們來應徵吧...
有點SystemVerilog, Verilog, 電路的基礎就可以丟了
地點是San Jose, CA
OPT可 意者請站內信



Responsibilities may include, but are not limited to:

· Partake in definition, design, verification, and documentation for
SoC System on a Chip development.

· Participate in architecture design, logic design, and system
simulation.

· Defines module interfaces/formats for simulation.

· Performs Logic design for integration of cell libraries, functional
units and subsystems into SoC full chip designs.

· Register transfer level coding, and simulation for SoCs.

· Contributes to the development of multidimensional designs involving
the layout of complex integrated circuits.

· Performs all aspects of the SoC design flow from high-level design
to synthesis, place and route, timing and power to create a design database
that is ready for manufacturing.

· Analyzes equipment to establish operation infrastructure, conducts
experimental tests, and evaluates results.

· May also review vendor capability to support development.



You must possess the minimum qualifications to be initially considered for
this position. Preferred qualifications are in addition to the minimum

requirements and are considered a plus factor in identifying top candidates.
Relevant experience can be obtained through school work, classes and

project work, internships, military training, and/ or work experience. This
is an entry level position and will be compensated accordingly.



Minimum Requirements:

· The candidate must possess a MS Degree in Electrical Engineering or
equivalent



Minimum 3 months experience in the following:

· Integrating IPs and cross-functioning with IP teams

· Hardware design, design verification, timing analysis, clock domain
crossing, and lint.



Preferred Qualifications:

· Knowledge of memory system design DDR4/DDR5/LPDDRx

· Knowledge of analog/mixed signal simulations SPICE/AMS

· Synthesis and Timing Closure flows, especially industry tools such
as Design Compiler and PrimeTime.

· Comfortable with scripting languages such as Perl,TCL

--

All Comments

Elvira avatar
By Elvira
at 2018-03-06T13:42
請問有類比嗎?
Ivy avatar
By Ivy
at 2018-03-11T08:10
Gary avatar
By Gary
at 2018-03-12T12:31
好像一年找一次?!
Jake avatar
By Jake
at 2018-03-16T13:26
請問有沒有opc
Kristin avatar
By Kristin
at 2018-03-18T05:28
Altera必推
Damian avatar
By Damian
at 2018-03-22T15:21
1目前履歷能直接拿給hiring manager的就這個職缺了
Dorothy avatar
By Dorothy
at 2018-03-27T07:30
問個比較特別的,intel有在做微機構之類的東西嗎
Bethany avatar
By Bethany
at 2018-04-01T06:24
可惜早一年有就好了

H1B跨州報稅(NY& CA)

Linda avatar
By Linda
at 2018-03-03T06:40
大家好 我是H1B第三年 2016/01/01-07/03 在紐約工作 得到一份W2, 收入A 2016/07/10-12/31 在加州工作 得到另一份W2, 收入B 聯邦稅方面我已經完成 州稅方面兩州都� ...

SDE in Test

Hazel avatar
By Hazel
at 2018-03-03T01:56
※ 引述《sean72 (.)》之銘言: : 最近拿到一個SDE in Test的phone screening : HR說部門主管想先做一個30分鐘的 and#34;chatand#34; : 但不是coding exersice : (實在不知道� ...

SDE in Test

Gary avatar
By Gary
at 2018-03-02T15:47
最近拿到一個SDE in Test的phone screening HR說部門主管想先做一個30分鐘的 and#34;chatand#34; 但不是coding exersice (實在不知道這個chat 是輕鬆的還是嚴肅的) 想請� ...

Material Research Engineer MS/PhD

Zora avatar
By Zora
at 2018-03-02T09:26
[公司]Bridgestone Americas [地點]Akron, Ohio [工作內容]Reinforcing materials research for tire and automotive application s. [網址]goo.gl/psmndk or search on bebridgestone.co ...

想請問 澳洲法律工作

William avatar
By William
at 2018-02-28T13:44
想請問有人在澳洲讀JD後在當地當律師的嗎? 我國立大學法律系去年畢業 考慮去澳洲讀JD後在澳洲當地執業並移民,也有朋友叫我去東歐讀醫學系 因為� ...