Marvell - Senior ASIC design engineer - 海外工作

MSEE with 5+ years of experience/PhD with working knowledge in following areas
preferred:

- Good understanding of DSP and communication building blocks
- Bluetooth, or other wireless baseband design/implementation experience
- Hand on lab experience to bringing up silicon sample
- Micro-architecture specification and verilog RTL coding
- Familiar with ASIC implementation flow: synthesis(DC), DFT, timing
closure(PT-SI), and formal verification
- Verification test bench development
- Excellent communication skills


Experience in following areas a plus:

- Matlab, C/C++, Perl, shell script, or TCL.
- System Verilog/VMM
- Interfacing with physical designer for floor planning/power optimization/
CTS/post layout timing closure.
- Mix signal and low power design.
- Complete product cycle experience from specification to production


Please send your resume to [email protected]

P.S. 還蠻急的.. 請有興趣的人將resume寄到上面信箱!

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