工作介紹-Physical Design Engineers, Shanghai, China - offer

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Job description 如下

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Our client, a Tier 1 Semiconductor company offers an opportunity to work

on a leading edge design project. Immediate,

long term permanent positions are available.

Responsible for full chip implementation of complex SOC’s (Netlist to GDS)

Work on full chip physical design in 45nm or below technologies.

3 year’s industry project level experience is required.

Must have Block Level tape out experience of complex chips @ 90 or 65nm.

The ability to speak and read English is a plus.

Experience with Cadence FirstEncounter is also a plus.

Relocation is not provided. Excellent competitive salary offered to

qualified candidates.

Qualified candidates please send resume to:

Mike Buckley
Sr. Recruiter
SYNAPSE Design Automation Inc.
[email protected]
www.synapse-da.com
Member of the Pinnacle Society - an elite consortium of 75 of the

nation's top recruiters http://www.pinnaclesociety.org/

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