影像IC設計疑問 - 工程師
By Dora
at 2017-02-13T01:41
at 2017-02-13T01:41
Table of Contents
推 bluemkevin: RTL 組合電路的部分用 gate level 似乎沒必要, Tool 02/12 18:48
→ bluemkevin: 會幫你化簡 02/12 18:48
其實我覺得這話也不是這麼講, tool好像是在Flip Flop之間化簡
combination電路的能力很強, 甚至我嘗試過寫到人都覺得長得不一樣的code,
netlist 就是硬生生的一樣, 讓我覺得千萬不要跟tool pk化簡, 因為你化不贏他
但是呢, 如果是架構上整個 FF可以少用的, 其實合成出來的就會天差地遠了(自己經驗)
以前好像曾經有個同事想要寫某段電路, 寫的落落長,
好像要做某種Bit shift還啥鬼的, 被我看穿意圖
他的Behavior code寫的落落長, 用掉一堆 Flip Flop
後來我把他code改成類似以下這種風格
A = {10, 01, 00, 11}
B = {A[3:0], A[7:4]}
A <= {B[1:0}, B[3:2], B[5:4], B[7:6]}
結果主管就把我電翻了XDDDD, 明明我的Code是對的, 而且Flip Flop 少三倍,
而且這Code又短又精簡很好呀XDD
面積又省一堆, 不過沒有人看的懂我想幹嘛=_=,
可是我覺得這明明就很簡單的數學規則而已
--
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工程師
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