應材宣布成功導入鈷材料取代銅,延續摩 - 工程師
By Kelly
at 2017-05-19T19:01
at 2017-05-19T19:01
Table of Contents
由於這是個很有意思的題目,所以我稍微搜尋了一下相關的文獻
又由於蔽人在下我的英文很爛,且這不在我的專業領域內,若有錯誤請幫忙指正,若是有
這方面專業者請不吝指教
我使用的初始關鍵字為cobalt damascene(以下我簡稱為鈷製程),然後由reference搜尋到
相關的文獻,大致上說的是copper damascene(以下簡稱銅製程)在10nm世代終結(這裡的世
代就如同台積的16,10,7nm,非指damascene的pitch)
雖然說銅的電阻率比鈷還低很多,但是銅製程中的阻障層(barrier)並不容易再減少厚度
,在銅電鍍的過程中會因為可填入銅的體積劇減,產生空隙(void)
因此10nm以下,需要改進阻障層的材質或是採用新的導體,也就是鈷
由於鈷可以使用無電電鍍底部成長型填充製程(electroless bottom up fill in),可以製
造
出無空隙(void free)導線,因次可藉次取代銅製程
對於一般半導體廠,銅製程依舊是最佳選擇,因為銅的電阻率比鈷低很多
對於台積、英特爾、***來說(我該提聯電嗎?),更先進的製程或許會採用鈷製程
而最有潛力的運用商,會是DRAM廠
在高深寬接觸窗( high aspect ratio contact)的金屬填充上,底部成長型填充是非常有
吸引力的誘因
以上,提供給想知道更多的人一點個人所知的訊息
--
又由於蔽人在下我的英文很爛,且這不在我的專業領域內,若有錯誤請幫忙指正,若是有
這方面專業者請不吝指教
我使用的初始關鍵字為cobalt damascene(以下我簡稱為鈷製程),然後由reference搜尋到
相關的文獻,大致上說的是copper damascene(以下簡稱銅製程)在10nm世代終結(這裡的世
代就如同台積的16,10,7nm,非指damascene的pitch)
雖然說銅的電阻率比鈷還低很多,但是銅製程中的阻障層(barrier)並不容易再減少厚度
,在銅電鍍的過程中會因為可填入銅的體積劇減,產生空隙(void)
因此10nm以下,需要改進阻障層的材質或是採用新的導體,也就是鈷
由於鈷可以使用無電電鍍底部成長型填充製程(electroless bottom up fill in),可以製
造
出無空隙(void free)導線,因次可藉次取代銅製程
對於一般半導體廠,銅製程依舊是最佳選擇,因為銅的電阻率比鈷低很多
對於台積、英特爾、***來說(我該提聯電嗎?),更先進的製程或許會採用鈷製程
而最有潛力的運用商,會是DRAM廠
在高深寬接觸窗( high aspect ratio contact)的金屬填充上,底部成長型填充是非常有
吸引力的誘因
以上,提供給想知道更多的人一點個人所知的訊息
--
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工程師
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