數位IC面試題目分享 - 面試
By Mia
at 2021-05-03T09:37
at 2021-05-03T09:37
Table of Contents
有個朋友在美國工作 豬屎屋RD經驗約8年 電機碩畢
好像因為想要拚看看更高職等跑去面試別家
雖然我覺得他現在已經領很多了 好眼紅XD
不囉嗦上試題
1. 請解釋Vt 對功耗的影響以及為什麼
2. 請問有沒有做過P-min flow (解釋: 用VCD 給P&R tool 吃進去專門降低公耗的)
請問這樣做主要是有那些優點跟缺點? 缺點如何改善?
3. short circuit current 是什麼? 要選用什麼Vt會比較好?
4. 請問lib file裡面的什麼值會決定這個flop的setup time?
5. 在一個大的SoC裡面常常靠近邊緣的兩個flop會有很大的clock skew 有哪些原因?
6. 用latch 有什麼好處跟壞處?
7. Multibit flop有那些好處跟壞處? 如何取捨?
這些題目我覺得比較小眾 不是給剛畢業的人的職缺
他說好像還要面幾關 有跟我分享題目然後我剛好很閒的話再PO給大家了~
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