聯詠面試問題 - 工程師
By Hedy
at 2015-06-03T14:44
at 2015-06-03T14:44
Table of Contents
借朋友帳號po文,願意提供資訊的也可站內信!
小妹是116電機學碩,近日要面談聯詠的APR實體設計工程師職位,有在版上搜尋過會考IC
design flow,set up/hold up time計算,CMOS電路,time constraint,wire load model
相關問題,面試前想複習一下相關概念,想尋問版上有沒有建議相關的參考書籍?
另外想請問會考C或verilog嗎?
非常感謝版上大大能提供相關資訊!
--
小妹是116電機學碩,近日要面談聯詠的APR實體設計工程師職位,有在版上搜尋過會考IC
design flow,set up/hold up time計算,CMOS電路,time constraint,wire load model
相關問題,面試前想複習一下相關概念,想尋問版上有沒有建議相關的參考書籍?
另外想請問會考C或verilog嗎?
非常感謝版上大大能提供相關資訊!
--
All Comments
By Tracy
at 2015-06-06T13:45
at 2015-06-06T13:45
By Delia
at 2015-06-08T05:51
at 2015-06-08T05:51
By Megan
at 2015-06-09T03:52
at 2015-06-09T03:52
By Lauren
at 2015-06-11T19:00
at 2015-06-11T19:00
By Carolina Franco
at 2015-06-12T13:47
at 2015-06-12T13:47
By Jacky
at 2015-06-16T21:19
at 2015-06-16T21:19
By Lauren
at 2015-06-19T20:41
at 2015-06-19T20:41
By Hedwig
at 2015-06-22T08:28
at 2015-06-22T08:28
By Olivia
at 2015-06-26T19:02
at 2015-06-26T19:02
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