[CTUAA] Job openning at Synopsys - 海外工作
By Blanche
at 2011-03-30T08:55
at 2011-03-30T08:55
Table of Contents
一樣也是代po喔...
==========================================================
Synopsys, a leading EDA company, is looking for candidates
with the following qualifications.
As the Corporate Applications Engineer (CAE) for the IC
Compiler product, you will serve as IC Compiler product
expert and provide support to customers, business partners,
internal sales channels, as well as R&D. The CAE will work
with R&D, marketing, and our customers to drive the development
and deployment of IC Compiler. The CAE will proactively
drive the team towards better design methodologies and
product features. Duties include technical training/presentation
creation and delivery, beta testing, documentation review,
demo creation, benchmarking, and more.
BSEE or MSEE with 1 ~ 3 years of relevant experience. Place &
Route experience is required. Must have used one or more of
the following tools: Design Compiler, Physical Compiler, Astro,
ICC, Cadence or Magma tools. Understanding of ASIC design
flow and design methodologies. Knowledge of competitive EDA
tool products and product knowledge in the areas of physical
synthesis, Place and Route. Good verbal and written communication
skills and ability to interface with customers and R&D are essential.
Strong communication skills are required. Must be proficient
with UNIX, Shell programming, TCL and Perl.
Please send your resume to Jennifer Liu ([email protected])
if you are interested in the position.
--
==========================================================
Synopsys, a leading EDA company, is looking for candidates
with the following qualifications.
As the Corporate Applications Engineer (CAE) for the IC
Compiler product, you will serve as IC Compiler product
expert and provide support to customers, business partners,
internal sales channels, as well as R&D. The CAE will work
with R&D, marketing, and our customers to drive the development
and deployment of IC Compiler. The CAE will proactively
drive the team towards better design methodologies and
product features. Duties include technical training/presentation
creation and delivery, beta testing, documentation review,
demo creation, benchmarking, and more.
BSEE or MSEE with 1 ~ 3 years of relevant experience. Place &
Route experience is required. Must have used one or more of
the following tools: Design Compiler, Physical Compiler, Astro,
ICC, Cadence or Magma tools. Understanding of ASIC design
flow and design methodologies. Knowledge of competitive EDA
tool products and product knowledge in the areas of physical
synthesis, Place and Route. Good verbal and written communication
skills and ability to interface with customers and R&D are essential.
Strong communication skills are required. Must be proficient
with UNIX, Shell programming, TCL and Perl.
Please send your resume to Jennifer Liu ([email protected])
if you are interested in the position.
--
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海外工作
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