台積EUV Litho RD Engineer - 工程師
By Bethany
at 2020-07-14T00:21
at 2020-07-14T00:21
Table of Contents
四大機械碩班,目前擔任非半導體產業的製程工程師,最近收到EUV Litho RD Engineer
的面試邀請,感到相當意外,因為從來都沒有想過可以當RD。但看板上好像說有些RD是負
責installation部分,但目前根據職務內容描述又不是,想知道實際大概的工作內容主要
為?若為機械背景會很吃力嗎?面試除了基本的半導體製程了解還需要特別準備什麼嗎?
主要是因為堆RD的了解太少了,謝謝大家。
職務說明:
1. Engage in EUV Scanner/Source projects collaborating with key suppliers 2. D
eep dive in plasma, particle, defect, laser, or vacuum technology 3. Work wit
h EUV Process team to deliver and sustain for advanced technology OR 3.Collabo
rate with RMESH/ISEP/FAC to introduce EUV production tool
--
的面試邀請,感到相當意外,因為從來都沒有想過可以當RD。但看板上好像說有些RD是負
責installation部分,但目前根據職務內容描述又不是,想知道實際大概的工作內容主要
為?若為機械背景會很吃力嗎?面試除了基本的半導體製程了解還需要特別準備什麼嗎?
主要是因為堆RD的了解太少了,謝謝大家。
職務說明:
1. Engage in EUV Scanner/Source projects collaborating with key suppliers 2. D
eep dive in plasma, particle, defect, laser, or vacuum technology 3. Work wit
h EUV Process team to deliver and sustain for advanced technology OR 3.Collabo
rate with RMESH/ISEP/FAC to introduce EUV production tool
--
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