Google台北 徵ASIC工程師 - 工程師

［代友po］格式如有不符合，請多多包涵

Google Taipei is looking for ASIC RTL Engineer & ASIC Design Verification Engi
neer, based in Taipei 101 office



（1)ASIC RTL Engineer, Consumer Hardware

［Responsibilities］
* Define the block level design document such as interface protocol, block dia
gram, transaction flow, pipeline, etc.
* Perform RTL coding, function/performance simulation debug, Lint/CDC/FV/UPF c
hecks.
* Participate in synthesis, timing/power closure and FPGA/silicon bring-up.
* Participate in test plan and coverage analysis of the block and SOC-level ve
rification.
* Communicate and work with multi-disciplined and multi-site teams.

［Qualifications］
-Minimum qualifications:
* BA/BS degree in Electrical Engineering or equivalent practical experience.
* 5 years of practical experience.
* Experience in ASIC development with Verilog or VHDL.
* Experience with ASIC design verification, synthesis, timing/power analysis a
nd DFT.
Preferred qualifications:
* MS degree in Electrical Engineering.
* 10 years of practical experience.
* Knowledge of high performance and low power design techniques. Knowledge of
assertion-based formal verification.
* Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture.
* Domain knowledge in one of these areas: memory compression, fabric, coherenc
e, cache, DRAM, PHY.
* Proficient with a scripting language like Perl.
#ASIC #RTL #Coding #Verilog #VHDL #Perl


（2)ASIC Design Verification Engineer, Consumer Hardware

［Responsibilities］
* Plan the verification of complex digital design blocks by fully understandin
g the design specification and interacting with design engineers to identify i
mportant verification scenarios.
* Create and enhance constrained-random verification environments using System
Verilog and UVM, or formally verify designs with SVA and industry leading form
al tools.
* Identify and write all types of coverage measures for stimulus and corner-ca
ses.
* Debug tests with design engineers to deliver functionally correct design blo
cks.
* Close coverage measures to identify verification holes and to show progress
towards tape-out.

［Qualifications］
-Minimum qualifications:
* BS degree in Electrical Engineering or Computer Science or equivalent practi
cal experience.
* Experience verifying digital logic at the Register Transfer Level (RTL) usin
g SystemVerilog for FPGAs, ASICs, and/or SoCs.
* Experience verifying complex digital systems, such as ones that use standard
IP components and interconnects, including microprocessor cores and hierarchi
cal memory subsystems.
* Experience with the creation of and usage of verification components and env
ironments in a standard verification methodology such as VMM, OVM, or UVM.

-Preferred qualifications:
* Master's or PhD degree in Electrical Engineering or Computer Science.
* 3 years of relevant work experience.
* Experience with image processing, computer vision, and/or machine learning a
pplications.
* Experience with performance verification of SoCs and SoC components and expe
rience with SoC standard interfaces and memory system architecture.
* Experience prototyping and debugging systems on Field Programmable Gate Arra
y (FPGA) platforms.
* Experience with verification of low power techniques.

—————————————————————
如果有符合，請聯絡下方資訊

Send English resume to >>>
[email protected]
[email protected]

The subject field of your email must include ASIC RTL Engineer or ASIC Design
Verification Engineer

HR Contact: Kino Tang
Mobile: +86 18301895930 (China)->I’m in Shanghai
+886 972865016 (Taiwan)
Email: [email protected]
[email protected]
https://www.linkedin.com/in/kinotang116/
https://bit.ly/2IsJ7fN

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